INSIDE the Laboratory

Laboratory for Brainware Systems

New Paradigm VLSI System Laboratory

Takahiro Hanyu, Professor
Masanori Natsui, Associate Professor

Rapid progress in the recent deep submicron regime has led to the capability to realize giga-scaled embedded systems on a chip (SoC), while the communication bottleneck between memory and logic modules has increasingly become a serious problem. In addition, power dissipation and device-characteristic variation have also been emerging problems in the recent very large-scaled integration (VLSI) chip. In order to solve these recent VLSI problems, which cause performance and reliability degradation, our research group focuses on a "new-paradigm VLSI computing" concept that investigates the opt imal design through a l l the VLSI design layer s f rom a device/material design level to an application-oriented algorithm level.

Figure 1

Figure 1 Nonvolatile TCAM Chip: Power supply at unmatched modules using perpendicular MTJ devices can be turned off. The search energy becomes 1/100 in comparison with that of the CPU implementation.

Figure 2

Figure 2 Nonvolatile Motion-Vector Prediction Chip: The chip is designed by using automated design tools for nonvolatile LSI. 75% of wasted power dissipation is eliminated by utilizing fine-grained nonvolatile power gating.

Figure 3

0.13μm CMOS 技術

Figure 3 Asynchronous NoC Router Chip: High-throughput compact delay-insensitive NoC router is fabricated based on an asynchronous-circuit aware packet structure.

As one of the latest research activities, we are focusing on a new VLSI architecture called "nonvolatile logic-in-memory (NV-LIM) architecture" and its design methodology. In this architecture, storage functions are distributed over a logic-circuit plane, which greatly reduces global wiring. To implement an NV-LIM LSI compactly, we utilize multi-functional and nonvolatile devices such as ferroelectric devices, magnetic tunnel junction (MTJ) devices and phase-change devices. We have proposed various applications based on NV-LIM architecture such as a ternary content-addressable memory (TCAM) chip (Fig.1) and a motion-vector prediction chip (Fig.2), and have confirmed the potential capability of NV-LIM LSI through fabrication and measurement under a national research project called “FIRST program” (project leader: Prof. Hideo Ohno). These results were announced at top-level international conferences on solid-state circuits such as ISSCC and VLSI Symposium, which clearly indicates the extremely high impact of our research activity on the related research communities.

We are also focusing on another challenging research subject concerning a new-paradigm VLSI computing system, that is, asynchronous data-transfer technique. Asynchronous design, where the timing constraint is limited locally, is one possible approach to solving today's serious interconnection problem, while maintaining low power dissipation, high speed and robustness. We have confirmed the capability of the proposed asynchronous system through the design and fabrication of concrete examples such as a low-energy asynchronous interleaver for clockless fully parallel low-density parity-check (LDPC) decoding and a delay-insensitive asynchronous network-onchip (NoC) router (Fig. 3), whose results were published in prestigious academic journals such as IEEE TCAS-I and IEEE Computer. VLSI processors and their application to a wide range of "smart" electronics systems, where VLSI processors are used as a "brain" for intelligent control like human beings, are key components in the recent information communication technology (ICT) society. In this research division, we explore a path towards a new-paradigm VLSI processor beyond brain, utilizing novel device technologies and newparadigm circuit architecture.

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